Program Schedule

Monday, November 7

Mon, Nov 7 | Tue, Nov 8 | Wed, Nov 9

Tutorial

9:00-10:30
TUTORIAL-1: Design of PLLs with Binary Phase Detectors for Frequency Synthesis & CDR
Asad Abidi
University of California, Los Angeles
10:50-12:20
TUTORIAL-2: Accelerating Deep Convolutional Neural Networks Using Specialized Hardware in the Datacenter
Joo-Young Kim
Microsoft Research
13:40-15:10
TUTORIAL-3: Wireless Systems from Link Budget to RFIC
Aarno Pärssinen
University of Oulu
15:30-17:00
TUTORIAL-4: Circuit Techniques for Serial Data Communications
Hirotaka Tamura
Fujitsu Laboratories Ltd.

Tuesday, November 8

Mon, Nov 7 | Tue, Nov 8 | Wed, Nov 9

Session 1: PLENARY SPEECH I

9:15-10:00
P1-1
Linear vs Adhocracy Innovation in Imaging, Networking and Computing
Mr. Amane Inoue
President & COO, Socionext Inc., Japan

Session 2: PLENARY SPEECH II

10:00-10:45
P2-1
A New Silicon Way: Generating Semiconductor-Intelligence Paradigm with a Virtual Moore's Law Economics and Heterogeneous Technologies
Dr. Nicky Lu
CTO and Founding Chairman, Etron Technology, Inc.
Chairman, Taiwan Semiconductor Industry Association, Taiwan

Session 3: LOW ENERGY DESIGNS AND ADVANCED INDUSTRY SOLUTIONS

Chair : Kazuko Nishimura, Panasonic Corporation
Co-Chair : Surhud Khare, Intel

11:05-11:30
S3-1 (4076)
A 3.2 mA-RX 3.5 mA-TX Fully Integrated SoC for Bluetooth Low Energy
M. Oshiro, T. Maruyama, T. Tokairin, Y. Tuda, T. Wang, N. Koide, Y. Ogasawara, T. Ta, H. Yoshida, K. Sami
Toshiba Corporation, Japan
11:30-11:55
S3-2 (4095)
A 2GS/s 8b Time-Interleaved SAR ADC for Millimeter-Wave Pulsed Radar Baseband SoC
T. Miki, T. Ozeki, J. Naka
Panasonic Corporation, Japan
11:55-12:20
S3-3 (4079)
20 mV Input, 4.2 V Output SIDO Boost Converter with Low-Power Controller and Adaptive Switch Size Selector for Thermoelectric Energy Harvesting
Y. Toyama, T. Ogawa, T. Ueno, T. Itakura
Toshiba Corporation, Japan
12:20-12:45
S3-4 (4171)
A High Efficiency Wide-Load-Range Asynchronous Boost Converter with Time-Based Dual-Mode Control for SSD Applications
K. Lee{1}, H. Kim{1}, J. Yoon{1}, H. Oh{1}, B. Park{1}, H. Park{1}, Y. Lee{2}
{1}Samsung Electronics, Korea; {2}Sungkyunkwan University, Korea
12:45-13:10
S3-5 (4232)
A 5.92-Mb/mm2 28-nm Pseudo 2-Read/Write Dual-Port SRAM Using Double Pumping Circuitry
Y. Ishii{2}, M. Yabuuchi{2}, Y. Sawada{1}, M. Morimoto{1}, Y. Tsukamoto{1}, Y. Yoshida{3}, K. Shibata{3}, T. Sano{3}, S. Tanaka{1}, K. Nii{2}
{1}Renesas Electronics, Japan; {2}Renesas Electronics / Kanazawa University, Japan; {3}Renesas System Design Co., Ltd., Japan

Session 4: INTELLIGENT CIRCUITS AND SYSTEMS

Chair : Jerald Yoo, Masdar Institute of Science and Technology
Co-Chair : Chao Wang, A*STAR

11:05-11:30
S4-1 (4205)
An 8-Bit, 16 Input, 3.2 pJ/op Switched-Capacitor Dot Product Circuit in 28-nm FDSOI CMOS
D. Bankman, B. Murmann
Stanford University, United States
11:30-11:55
S4-2 (4077)
Time-Domain Neural Network: a 48.5 TSOp/s/W Neuromorphic Chip Optimized for Deep Learning and CMOS Technology
D. Miyashita, S. Kousai, T. Suzuki, J. Deguchi
Toshiba Corporation, Japan
11:55-12:20
S4-3 (4012)
A Series-SSHI-Phi Interface Circuit for Piezoelectric Energy Harvesting with 163% Improvement in Extracted Power at Off-Resonance
C. Chen{2}, H. Chen{2}, Y. Huang{2}, P. Hsieh{2}, P. Wu{1}, Y. Shu{1}
{1}National Taiwan University, Taiwan; {2}National Tsing Hua University, Taiwan
12:20-12:45
S4-4 (4236)
An Area-Efficient Wideband CMOS Hall Sensor System for Camera Autofocus Systems
C. Tu{2}, K. Chen{2}, T. Wu{1}, T. Lin{2}
{1}Himax Technologies Inc., Taiwan; {2}National Taiwan University, Taiwan
12:45-12:57
S4-5 (4143)
A Time Delay Multiple Integration Linear CMOS Image Sensor for Multispectral Satellite Telemetry
K. Liu{2}, C. Hsieh{2}, S. Lai{1}, C. Chiu{1}
{1}National Chip Implementation Center, Taiwan; {2}National Tsing Hua University, Taiwan
12:57-13:09
S4-6 (4192)
An Inductive-Coupling Bus with Collision Detection Scheme Using Magnetic Field Variation for 3-D Network-on-Chips
J. Kadomoto, T. Miyata, H. Amano, T. Kuroda
Keio University, Japan

Session 5: ANALOG TECHNIQUES

Chair : Seung-Tak Ryu, KAIST
Co-Chair : Po-Chiun Huang, National Tsing Hua University

14:20-14:45
S5-1 (4239)
A 40-nV/√Hz 0.0145-mm2 Sensor Readout Circuit with Chopped VCO-Based CTDSM in 40-nm CMOS
C. Tu, Y. Wang, T. Lin
National Taiwan University, Taiwan
14:45-15:10
S5-2 (4101)
56-Level Programmable Voltage Detector in Steps of 50mV for Battery Management
T. Someya{2}, K. Matsunaga{1}, H. Morimura{1}, T. Sakurai{2}, M. Takamiya{2}
{1}Nippon Telegraph and Telephone Corporation, Japan; {2}University of Tokyo, Japan
15:10-15:35
S5-3 (4067)
93% Efficiency and 0.99 Power Factor in Pseudo-Linear LED Driver
S. Chiu{2}, C. Kuo{2}, K. Chuang{1}, W. Yang{1}, K. Chen{1}, C. Wey{1}, Y. Lin{3}, J. Lin{3}, T. Tsai{3}, J. Chen{4}
{1}National Chiao Tung University, Taiwan; {2}National Chiao Tung University / Anwell Corp., Taiwan; {3}Realtek Semiconductor Corp., Taiwan; {4}Vanguard Semiconductor Corp, Taiwan
15:35-15:47
S5-4 (4085)
A High DR Multi-Channel Stage-Shared Hybrid Front-End for Integrated Power Electronics Controller
Y. Ren, S. Sin, C. Lam, M. Wong, S. U, R. Martins
University of Macau, Macau
15:47-15:59
S5-5 (4215)
An OTA-C Signal Processing FPAA with 305 MHz GBW and Integrated Frequency-Independent Filter Tuning
D. De Dorigo, Y. Manoli
Albert-Ludwigs-Universität Freiburg, Germany

Session 6: HIGH-SPEED ADCS

Chair : Jintae Kim, Konkuk University
Co-Chair : Jong-Woo Lee, Samsung Electronics

14:20-14:45
S6-1 (4068)
A 9-Bit 500-MS/s 6.0-mW Dynamic Pipelined ADC Using Time-Domain Linearized Dynamic Amplifiers
L. Yu, M. Miyahara, A. Matsuzawa
Tokyo Institute of Technology, Japan
14:45-15:10
S6-2 (4178)
An 8-Bit 1.25GS/s CMOS IF-Sampling ADC with Background Calibration for Dynamic Distortion
S. Chen, B. Murmann
Stanford University, United States
15:10-15:35
S6-3 (4054)
A 10-b 800MS/s Time-Interleaved SAR ADC with Fast Timing-Skew Calibration
J. Song, K. Ragab, X. Tang, N. Sun
University of Texas at Austin, United States
15:35-15:47
S6-4 (4138)
A 10-Bit 1GS/s 4-Way TI SAR ADC with Tapinterpolated FIR Filter Based Time Skew Calibration
L. Qiu{1}, T. Kai{1}, Y. Zhu{2}, L. Siek{1}, Y. Zheng{1}, S. U{2}
{1}Nanyang Technological University, Singapore; {2}University of Macau, China
15:47-15:59
S6-5 (4036)
A 0.9V 15fJ/Conversion-Step 8-Bit 1.5GS/s Two-Step SAR ADC
Y. Hu, P. Huang, M. Yang, S. Wu, H. Chen
National Taiwan University, Taiwan

Session 7: BUILDING BLOCKS FOR WIRELINE COMMUNICATIONS

Chair : Jun Terada, NTT
Co-Chair : Ching-Yuan Yang, National Chung-Hsing University

14:20-14:45
S7-1 (4141)
An Improved 40 Gb/s CDR with Jitter-Suppression Filters and Phase-Compensating Interpolators
X. Zheng{1}, C. Zhang{1}, S. Yuan{1}, F. Zhao{2}, S. Yue{2}, Z. Wang{1}, F. Li{1}, Z. Wang{1}
{1}Tsinghua University, China; {2}University of Lincoln, United Kingdom
14:45-15:10
S7-2 (4187)
Fractional-N DPLL Based Low Power Clocking Architecture for 1-14 Gb/s Multi-Standard Transmitter
M. Hossain, A. Nag, W. El-Halwagy, A. Hossain, -. Aurangozeb
University of Alberta, Canada
15:10-15:35
S7-3 (4169)
A 4-GHz ΔΣ Fractional-N Frequency Synthesizer with 2-Dimensional Quantization Noise Pushing and Fractional Spur Elimination Techniques
C. Lin, T. Lin
National Taiwan University, Taiwan
15:35-15:47
S7-4 (4053)
A 14.4Gb/s/pin 230fJ/b/pin/mm Multi-Level RFInterconnect for Global Network-on-Chip Communication
M. Jalalifar, G. Byun
Southern Methodist University, United States
15:47-15:59
S7-5 (4038)
A Digital MDLL Using Switched Biasing Technique to Reduce Low-Frequency Phase Noise
C. Chiang{2}, C. Huang{1}, T. Kuan{3}, S. Liu{1}
{1}National Taiwan University, Taiwan; {2}Novatek, Taiwan; {3}Taiwan Semiconductor Manufacturing Company, Limited, Taiwan

Session 8: RF TRANSCEIVERS

Chair : Taizo Yamawaki, Hitachi
Co-Chair : Chien-Nan Kuo, National Chao Tung University

14:20-14:45
S8-1 (4040)
A 79GHz 2x2 MIMO PMCW Radar SoC in 28nm CMOS
D. Guermandi, Q. Shi, A. Dewilde, V. Derudder, U. Ahmad, A. Spagnolo, A. Bourdoux, P. Wambacq, W. Van Thillo
IMEC, Belgium
14:45-15:10
S8-2 (4194)
An Lo-Buffer-Less 60-GHz CMOS Transmitter with Oscillator Pulling Mitigation
R. Wu, J. Pang, Y. Seo, K. Kimura, S. Kawai, S. Sato, S. Kondo, T. Ueno, N. Fajri, Y. Takeuchi, T. Yamaguchi, A. Musa, M. Miyahara, K. Okada, A. Matsuzawa
Tokyo Institute of Technology, Japan
15:10-15:35
S8-3 (4211)
Low Power FSK Transceiver Using ADPLL with Direct Modulation and Integrated SPDT for BLE Application
D. Lee{4}, S. Oh{4}, S. Kim{4}, C. Lee{4}, C. Song{4}, J. Kim{4}, W. Kim{4}, H. Kim{4}, S. Yoo{2}, S. Hong{1}, J. Lee{3}, Y. Pu{4}, K. Lee{4}
{1}ABOV Semiconductor Co., Ltd., Korea; {2}Korea Advanced Institute of Science and Technology, Korea; {3}Nplanic, Korea; {4}Sungkyunkwan University, Korea
15:35-16:00
S8-4 (4119)
Highly Linear TIA for SAW-Less FDD Receivers
G. Pini, D. Manstretta, R. Castello
Università degli Studi di Pavia, Italy

Session 9: PANEL DISCUSSION

Chair : Toru Shimizu, Keio University

16:20-18:00
AI (Artificial Intelligence) and SoC

Wednesday, November 9

Mon, Nov 7 | Tue, Nov 8 | Wed, Nov 9

Session 10: PLENARY SPEECH III

9:00-9:45
P10-1
Let Anyone Experience Tangible Intelligence
Dr. Sungwoo Hwang
Head, Device & System Research Center, Samsung Advanced Institute of Technology, Korea

Session 11: PLENARY SPEECH IV

9:45-10:30
P11-1
The Doctor Prescribes Silicon - Healthcare in the 21st Century
Prof. Chris Van Hoof
IMEC Director, Wearable Health Solutions, IMEC Fellow, Belgium

Session 12: EFFICIENCY AND RELIABILITY ENHANCEMENT IN DIGITAL SYSTEMS

Chair : Jun Zhou, A*STAR
Co-Chair : Chia-Hsiang Yang, National Taiwan University

10:50-11:15
S12-1 (4064)
Reprogrammable Redundancy for Cache Vmin Reduction in a 28nm RISC-V Processor
B. Zimmer, P. Chiu, B. Nikolić, K. Asanović
University of California, Berkeley, United States
11:15-11:40
S12-2 (4044)
On-Chip Supply Power Measurement and Waveform Reconstruction in a 28nm FD-SOI Processor SoC
M. Cochet{4}, A. Puggelli{5}, B. Keller{5}, B. Zimmer{5}, M. Blagojevic{3}, S. Clerc{2}, P. Roche{5}, J. Autran{1}, B. Nikolić{5}
{1}Aix-Marseille Université, France; {2}STMicroelectronics, France; {3}STMicroelectronics / University of California, Berkeley, France; {4}STMicroelectronics / University of California, Berkeley / Aix-Marseille Université, France; {5}University of California, Berkeley, France; {5}University of California, Berkeley, United States
11:40-12:05
S12-3 (4176)
A 0.35V 1.3pJ/Cycle 20MHz 8-Bit 8-Tap FIR Core Based on Wide-Pulsed-Latch Pipelines
W. Jin{3}, S. Kim{1}, W. He{2}, Z. Mao{2}, M. Seok{1}
{1}Columbia University, United States; {2}Shanghai Jiao Tong University, China; {3}Shanghai Jiao Tong University / Columbia University, United States
12:05-12:30
S12-4 (4165)
A 5.5GHz 0.84TOPS/mm2 Neural Network Engine with Stream Architecture and Resonant Clock Mesh
S. Lu, Z. Zhang, M. Papaefthymiou
University of Michigan, United States
12:30-12:42
S12-5 (4137)
Area-Efficient One-Cycle Correction Scheme for Timing Errors in Flip-Flop Based Pipelines
J. Koo{1}, E. Song{1}, E. Park{2}, D. Kim{2}, J. Park{1}, S. Ryu{1}, S. Yoo{2}, J. Kim{1}
{1}Pohang University of Science and Technology, Korea; {2}Seoul National University, Korea
12:42-12:54
S12-6 (4168)
A 5.1Gb/s 60.3fJ/bit/mm PVT Tolerant NoC Transceiver
V. Kulkarni, W. Lim, B. Zhao, D. Yan, Y. Wang, J. Zhou, M. Arasu
Agency for Science, Technology and Research, Singapore

Session 13: NYQUIST ADCS

Chair : Takeshi Yoshida, Hiroshima University
Co-Chair : Sanroku Tsukamoto, Fujitsu Laboratories Ltd.

10:50-11:15
S13-1 (4047)
A 0.011mm2 60dB SNDR 100MS/s Reference Error Calibrated SAR ADC with 3pF Decoupling Capacitance for Reference Voltages
C. Chan, Y. Zhu, I. Ho, W. Zhang, C. Lio, S. U, R. Martins
University of Macau, Macau
11:15-11:40
S13-2 (4037)
A 12-Bit 200kS/s Subranging SAR ADC with an Energy-Curve Reshape Technique
Y. Hu, K. Lin, H. Chen
National Taiwan University, Taiwan
11:40-12:05
S13-3 (4158)
A 16 Bit Linear Passive-Charge-Sharing SAR ADC in 55nm CMOS
M. Maddox, B. Chen, M. Coln, R. Kapusta, J. Shen, L. Fernando
Analog Devices, Inc, United States
12:05-12:30
S13-4 (4113)
A 12 Bit 150 MS/s 1.5 mW SAR ADC with Adaptive Radix DAC in 40 nm CMOS
K. Chang, C. Hsieh
National Tsing Hua University, Taiwan
12:30-12:55
S13-5 (4204)
A 4.86 mW 15-Bit 22.5 MS/s Pipelined ADC with 74 dB SNDR in 90 nm CMOS Using Averaging Correlated Level Shifting Technique
T. Hung, T. Kuo
National Cheng Kung University, Taiwan

Session 14: INTELLIGENT MEMORIES

Chair : Atsushi Kawasumi, Toshiba Corporation
Co-Chair : Hwang Hur, SK hynix

10:50-11:15
S14-1 (4091)
Design Challenge in 3D NAND Technology: a 4.8X Area- and 1.3X Power-Efficient 20V Charge Pump Using Tier Capacitors
T. Tanzawa{1}, T. Murakoshi{1}, T. Kamijo{1}, T. Tanaka{1}, J. McNeil{2}, K. Duesman{2}
{1}Micron Memory Japan, Inc., Japan; {2}Micron Technology, Inc., United States
11:15-11:40
S14-2 (4041)
Design of Non-Contact 2Gb/s I/O Test Methods for High Bandwidth Memory (HBM)
H. Lee, S. Kang, H. Yu, W. Yun, J. Jung, S. Ahn, W. Kim, B. Kil, Y. Sung, S. Shin, Y. Park, Y. Kim, K. Nam, I. Song, K. Sohn, Y. Bae, J. Choi, S. Jang, G. Jin
Samsung Electronics, Korea
11:40-12:05
S14-3 (4084)
A 0.3 pJ/Access 8T Data-Aware SRAM Utilizing Column-Based Data Encoding for Ultra-Low Power Applications
A. Do{1}, S. Zeinolabedin{2}, T. Kim{2}
{1}Agency for Science, Technology and Research, Singapore; {2}Nanyang Technological University, Singapore
12:05-12:30
S14-4 (4193)
Reconfigurable, Conditional Pre-Charge SRAM: Lowering Read Power by Leveraging Data Statistics
C. Duan{1}, A. Gotterba{2}, M. Sinangil{2}, A. Chandrakasan{1}
{1}Massachusetts Institute of Technology, United States; {2}Nvidia Corporation, United States
12:30-12:42
S14-5 (4174)
A Double-Tail Sense Amplifier for Low-Voltage SRAM in 28nm Technology
P. Chiu, B. Zimmer, B. Nikolić
University of California, Berkeley, United States
12:42-12:54
S14-6 (4058)
A 64-Kb 0.37V 28nm 10T-SRAM with Mixed-Vth Read-Port and Boosted WL Scheme for IoT Applications
H. Fujiwara, Y. Chen, C. Lin, W. Wu, D. Sun, S. Wu, H. Liao, J. Chang
Taiwan Semiconductor Manufacturing Company, Limited, Taiwan

Session 15: BIOMEDICAL CIRCUITS AND SYSTEMS

Chair : Noriyuki Miura, Kobe Univeristy
Co-Chair : Youngcheol Chae, Yonsei University, Korea

10:50-11:15
S15-1 (4240)
A 2.34µJ/Scan Acoustic Power Scalable Charge-Redistribution pMUT Interface System with on-Chip Aberration Compensation for Portable Ultrasonic Applications
J. Tillak{1}, S. Akhbari{2}, N. Shah{1}, L. Radakovic{1}, L. Lin{2}, J. Yoo{1}
{1}Masdar Institute of Science and Technology, U.A.E.; {2}University of California, Berkeley, United States
11:15-11:40
S15-2 (4218)
An EEG-NIRS Ear-Module SoC for Wearable Drowsiness Monitoring System
U. Ha, H. Yoo
Korea Advanced Institute of Science and Technology, Korea
11:40-12:05
S15-3 (4144)
An Integrated CMOS Optical Sensing Chip for Multiple Bio-Signal Detections
A. Chiou, S. Hsieh, Y. Pan, C. Kuo, C. Hsieh
National Tsing Hua University, Taiwan
12:05-12:30
S15-4 (4027)
A 1.1mW Hybrid OFDM Ground Effect-Resilient Body Coupled Communication Transceiver for Head and Body Area Network
W. Saadeh{1}, H. Alsuradi{2}, M. Altaf{1}, J. Yoo{2}
{1}Lahore University of Management Sciences, Pakistan; {2}Masdar Institute of Science and Technology, U.A.E.
12:30-12:42
S15-5 (4135)
A 83% Peak Efficiency 1.65V to 11.4V Dynamic Voltage Scaling Supply for Electrical Stimulation Applications in Standard 0.18µm CMOS Process
L. Yao{1}, D. Made{1}, Y. Gao{2}
{1}Agency for Science, Technology and Research, Singapore; {2}Agency for Science, Technology and Research / Nanyang Technological University, Singapore
12:42-12:54
S15-6 (4162)
A 13.56 MHz, 162 mW Magnetically Coupled Digital Rectifier with 94% VCR, 96% PCE Over 50-to-5K Ω Load Range, and Embedded 80 kbps DBPSK Demodulator for Biomedical Applications
H. Cruz, S. Lee, C. Luo
National Cheng Kung University, Taiwan

Session 16: DC-DC CONVERTERS

Chair : Nobukazu Takai, Gunma University
Co-Chair : Po-Hung Chen, National Chiao Tung University

14:20-14:45
S16-1 (4066)
All-Digital Single-Inductor Multiple-Output DC-DC Converter with Over 65.3% Efficiency in 1 uW to 50 mW Load Range and 86.3% Peak Efficiency
M. Yamada, N. Tran, T. Miyazaki, Y. Yoshihara, R. Fujimoto
Toshiba Corporation, Japan
14:45-15:10
S16-2 (4074)
Multiple-Loop Design Technique for High-Performance Low Dropout Regulator
Q. Duong, J. Kong, H. Shin, H. Nguyen, P. Kim, Y. Ko, H. Yu, H. Park
Samsung Electronics, Korea
15:10-15:35
S16-3 (4212)
A 90nA Quiescent Current 1.5V-5V 50mA Asynchronous Folding LDO Using Dual Loop Control
J. Liu{2}, T. Bryant{2}, N. Maghari{2}, J. Morroni{1}
{1}Texas Instruments, United States; {2}University of Florida, United States
15:35-15:47
S16-4 (4196)
A 0.38-µW Stand-by Power, 50-nA-to-1-mA Load Current Range DC-DC Converter with Self-Biased Linear Regulator for Ultra-Low Power Battery Management
T. Ozaki, T. Hirose, H. Asano, N. Kuroki, M. Numa
Kobe University, Japan
15:47-15:59
S16-5 (4220)
An Area Efficient Single-Cycle xVDD Sub-Vth on-Chip Boost Scheme in 28 nm FD-SOI
B. Mohammadi, O. Andersson, X. Luo, M. Nouripayam, J. Neves Rodrigues
Lund University, Sweden

Session 17: WIRELINE TRANSMITTER TECHNIQUES

Chair : Samuel Palermo, Texas A&M University
Co-Chair : Yasufumi Sakai, Fujitsu Laboratories Ltd.

14:20-14:45
S17-1 (4153)
A 32.75-Gb/s Voltage Mode Transmitter with 3-Tap FFE in 16nm CMOS
K. Chan{1}, K. Tan{1}, Y. Frans{2}, J. Im{2}, P. Upadhyaya{2}, S. Lim{1}, A. Roldan{1}, N. Narang{1}, C. Koay{1}, H. Zhao{1}, K. Chang{2}
{1}Xilinx Singapore, Singapore; {2}Xilinx, Inc., United States
14:45-15:10
S17-2 (4126)
A Model Predictive Control Equalization Transmitter for Asymmetric Interfaces in 28nm FDSOI
T. Kim, P. Bhargava, V. Stojanović
University of California, Berkeley, United States
15:10-15:35
S17-3 (4015)
A 6-to-32 Gb/s Voltage-Mode Transmitter with Scalable Supply, Voltage Swing, and Pre-Emphasis in 65-nm CMOS
W. Bae, H. Ju, K. Park, D. Jeong
Seoul National University, Korea
15:35-15:47
S17-4 (4177)
All-Synthesizable 6Gbps Voltage-Mode Transmitter for Serial Link
Y. Choi, K. Seong, B. Kim, J. Sim, H. Park
Pohang University of Science and Technology, Korea
15:47-15:59
S17-5 (4059)
A 5-8 Gb/s Low-Power Transmitter with 2-Tap Pre-Emphasis Based on Toggling Serialization
S. Kim, T. Kim, D. Kwon, W. Choi
Yonsei University, Korea

Session 18: SOCS FOR RECOGNITION & LEARNING

Chair : Satoshi Shigematsu, NTT
Co-Chair : Shigeki Tomishima, Intel

14:20-14:45
S18-1 (4100)
A 305mV-850mV 400µW 45GSamples/J Reconfigurable Compressive Sensing Engine with Early-Termination for Ultra-Low Energy Target Detection in 14nm Tri-Gate CMOS
S. Satpathy, S. Mathew, V. Suresh, M. Anders, G. Chen, H. Kaul, A. Agarwal, S. Hsu, R. Krishnamurthy, V. De
Intel Corporation, United States
14:45-15:10
S18-2 (4123)
A 34pJ/Level Pixel Depth-Estimation Processor with Shifter-Based Pipelined Architecture for Mobile User Interface
S. Choi, S. Park, H. Yoo
Korea Advanced Institute of Science and Technology, Korea
15:10-15:35
S18-3 (4217)
A Low-Power Real-Time Hidden Markov Model Accelerator for Gesture User Interface on Wearable Devices
S. Choi, J. Hwang, S. Cho, A. Kim, B. Nam
Chungnam National University, Korea
15:35-16:00
S18-4 (4183)
A 41.3pJ/26.7pJ Per Neuron Weight RBM Processor for on-Chip Learning/Inference Applications
C. Tsai{1}, W. Yu{1}, W. Wong{2}, C. Lee{1}
{1}National Chiao Tung University, Taiwan; {2}Stanford University, United States

Session 19: FREQUENCY SYNTHESIS AND TRANSMITTER TECHNIQUES

Chair : Chun-Huat Heng, National University of Singapore
Co-Chair : Davide Guermandi, IMEC

14:20-14:45
S19-1 (4191)
A Low-Power Calibration-Free Fractional-N Digital PLL with High Linear Phase Interpolator
F. Yang, H. Guo, R. Wang, Z. Zhang, J. Liu, H. Liao
Peking University, China
14:45-15:10
S19-2 (4070)
A Technique for in-Band Phase Noise Reduction in Fractional-N Frequency Synthesizers
C. Wang, T. Lee
National Taiwan University, Taiwan
15:10-15:35
S19-3 (4186)
A 1.9mW 750kB/s 2.4GHz F-OOK Transmitter with Symmetric FM Template and High-Point Modulation PLL
Y. Zhang, R. Zhou, W. Rhee, Z. Wang
Tsinghua University, China
15:35-15:47
S19-4 (4226)
Lossless Inductor Current Control in Envelope Tracking Supply Modulator with Self-Allocation of Energy for Optimzation of Efficiency and EVM
S. Yang{1}, K. Chen{1}, C. Wey{1}, Y. Lin{2}, J. Lin{2}, T. Tsai{2}
{1}National Chiao Tung University, Taiwan; {2}Realtek Semiconductor Corp., Taiwan
15:47-15:59
S19-5 (4082)
A Single-Event Upset Robust, 2.2 GHz to 3.2 GHz, 345 fs Jitter PLL with Triple-Modular Redundant Phase Detector in 65 nm CMOS
J. Prinzie{2}, M. Steyaert{2}, P. Leroux{2}, J. Christiansen{1}, P. Moreira{1}
{1}European Organization for Nuclear Research, Switzerland; {2}Katholieke Universiteit Leuven, Belgium

Session 20: ENERGY HARVESTING

Chair : Takeshi Ueno, Toshiba Corporation
Co-Chair : Sai-Weng Sin, University of Macau

16:20-16:45
S20-1 (4120)
Triple-Mode Photovoltaic Power Management: Achieving High Efficiency Against Harvesting and Load Variability
J. Li{2}, J. Seo{1}, I. Kymissis{2}, M. Seok{2}
{1}Arizona State University, United States; {2}Columbia University, United States
16:45-17:10
S20-2 (4208)
A Single-Inductor Dual-Input Dual-Output (SIDIDO) Power Management with Sequential Pulse-Skip Modulation for Battery/PV Hybrid Systems
H. Lee, P. Chen
National Chiao Tung University, Taiwan
17:10-17:35
S20-3 (4172)
An Isolated Por Based Pulse Generator for TEG Energy Harvesting with Minimum Startup of 150 mV and Maximum Series Resistance of 600 Ω
A. Das{2}, Y. Gao{1}, T. Kim{2}
{1}Agency for Science, Technology and Research / Nanyang Technological University, Singapore; {2}Nanyang Technological University, Singapore
17:35-17:47
S20-4 (4154)
Ultra-Low Voltage Ripple in DC-DC Boost Converter by the Pumping Capacitor and Wire Inductance Technique
C. Tang{1}, K. Chen{1}, C. Wey{1}, Y. Lin{2}, J. Lin{2}, T. Tsai{2}
{1}National Chiao Tung University, Taiwan; {2}Realtek Semiconductor Corp., Taiwan
17:47-17:59
S20-5 (4139)
A Piezoelectric Vibration Energy Harvesting System with Improved Power Extraction Capability
Y. Hu, I. Chen, T. Tsai
National Chung Cheng University, Taiwan

Session 21: OVERSAMPLING AND TIME-DOMAIN CONVERTERS

Chair : Tsung-Heng Tsai, National Chung Cheng University
Co-Chair : Liyuan Liu, Chinese Academy of Sciences

16:20-16:45
S21-1 (4142)
A 2nd Order Fully-Passive Noise-Shaping SAR ADC with Embedded Passive Gain
Z. Chen, M. Miyahara, A. Matsuzawa
Tokyo Institute of Technology, Japan
16:45-17:10
S21-2 (4086)
A Fine-Resolution Pulse-Shrinking Time-to-Digital Converter with Completion Detection Utilizing Built-in Offset Pulse
T. Iizuka, T. Koga, T. Nakura, K. Asada
University of Tokyo, Japan
17:10-17:35
S21-3 (4023)
A 91.2dB SNDR 66.2fJ/Conv. Dynamic Amplifier Based 24kHz ΔΣ Modulator
B. Zhang, R. Dou, L. Liu, N. Wu
Chinese Academy of Sciences, China
17:35-17:47
S21-4 (4222)
A 79dB SNDR, 10MHz BW, 675MS/s Open-Loop Time-Based ADC Employing a 1.15ps SAR-TDC
W. El-Halwagy, P. Mousavi, M. Hossain
University of Alberta, Canada
17:47-17:59
S21-5 (4148)
A 50 MHz Bandwidth 54.2 dB SNDR Reference-Free Stochastic ADC Using VCO-Based Quantizers
H. Sun{2}, J. Muhlestein{2}, S. Leuenberger{2}, K. Sobue{1}, K. Hamashita{1}, U. Moon{2}
{1}Asahi Kasei Microdevices, United States; {2}Oregon State University, United States

Session 22: ENERGY-EFFICIENT TECHNIQUES FOR SOC

Chair : Pei-Yun Tsai, National Central University
Co-Chair : Yong Lian, York University

16:20-16:45
S22-1 (4244)
A 65-nm 0.35-V 7.1-µW Memory-Less Adaptive PCG Processor for Wearable Long-Term Cardiac Monitoring
C. Wang{1}, J. Zhang{2}, J. Zhou{1}, X. Liu{1}, R. Tan{3}, L. Zhong{3}, K. Chai{1}
{1}Agency for Science, Technology and Research, Singapore; {2}Nanyang Technological University, Singapore; {3}National Heart Centre Singapore, Singapore
16:45-17:10
S22-2 (4031)
A 28 nm CMOS 7.04 Gsps Polar Digital Front-End Processor for 60 GHz Transmitter
Y. Huang{1}, C. Li{1}, K. Khalaf{1}, A. Bourdoux{1}, J. Verschueren{1}, Q. Shi{1}, P. Wambacq{1}, S. Pollin{2}, W. Dehaene{2}, L. Van der Perre{2}
{1}IMEC, Belgium; {2}Katholieke Universiteit Leuven, Belgium
17:10-17:35
S22-3 (4088)
A 7.72 Gb/s LDPC-CC Decoder with Overlapped Architecture for Pre-5G Wireless Communications
C. Lin, R. Liu, C. Chen, H. Chang, C. Lee
National Chiao Tung University, Taiwan
17:35-18:00
S22-4 (4105)
1.68µJ/Signature-Generation 256-Bit ECDSA Over GF(p) Signature Generator for IoT Devices
M. Tamura, M. Ikeda
University of Tokyo, Japan

Session 23: RF BUILDING BLOCKS

Chair : Minoru Fujishima, Hiroshima University
Co-Chair : Ting-Ping Liu, Nokia

16:20-16:45
S23-1 (4152)
A 32.9% PAE, 15.3 dBm, 21.6-41.6 GHz Power Amplifier in 65nm CMOS Using Coupled Resonators
H. Jia{1}, C. Prawoto{1}, B. Chi{2}, Z. Wang{2}, P. Yue{1}
{1}Hong Kong University of Science and Technology, Hong Kong; {2}Tsinghua University, China
16:45-17:10
S23-2 (4190)
A 16-43 GHz Low-Noise Amplifer with 2.5-4.0 dB Noise Figure
Z. Chen{2}, H. Gao{2}, D. Leenaerts{1}, D. Milosevic{2}, P. Baltus{2}
{1}NXP Semiconductors, Netherlands; {2}Technische Universiteit Eindhoven, Netherlands
17:10-17:35
S23-3 (4202)
A 7.9-GHz Transformer-Feedback Quadrature VCO with a Noise-Shifting Coupling Network
B. Jiang{2}, C. Chen{1}, J. Ren{1}, H. Luong{2}
{1}Fudan University, China; {2}Hong Kong University of Science and Technology, Hong Kong
17:35-18:00
S23-4 (4167)
Transformer-Based Varactor-Less 96GHz-110GHz VCO and 89GHz-101GHz QVCO in 65nm CMOS
X. Liu{2}, C. Chen{1}, J. Ren{1}, H. Luong{2}
{1}Fudan University, China; {2}Hong Kong University of Science and Technology, Hong Kong